1. Field of the Invention
This invention relates generally to servers and more particularly to a processor architecture and method for serving data to client computers over a network.
2. Description of the Related Art
With the networking explosion brought along with introduction of the Internet, there has been a shift from the single thread desktop applications for personal computers to server applications that have multiple threads for serving multiple clients. Electronic commerce has created a need for large enterprises to serve potentially millions of customers. In order to support this overwhelming demand, the serving applications require different memory characteristics than the memory characteristics for desktop applications. In particular, the serving applications require large memory bandwidth and large cache memory requirements in order to accommodate a large number of clients.
In addition, conventional processors focus on instruction level parallelism. Therefore, the processors tend to be very large and the pipeline is very complex. Consequently, due to the complexity of the pipeline for processors, such as INTEL processors, only one core is on the die. Accordingly, when there is a cache miss or some other long latency event, there is usually a stall that causes the pipeline to sit idle. Serving applications are generally constructed to be more efficient with very little instruction level parallelism per thread. Thus, the characteristics of implementation for conventional processors with the application of serving workloads result in a poor fit since conventional processors focus on instruction level parallelism.
Additionally, the performance of processors based on instruction level parallelism (ILP), as a function of die size, power and complexity, is reaching a saturation point. Conventional ILP processors include well known processors from the PENTIUM™, ITANIUM™, ULTRASPARC™, etc., families. Thus, in order to increase performance, future processors will have to move away from the traditional ILP architecture.
In view of the forgoing, there is a need for a processor having an architecture better suited for serving applications in which the architecture is configured to exploit multi-thread characteristics of serving applications.